FIG. 1 shows a conventional repeater architecture 10. Repeater 10 is configured to receive and transmit serial data streams between two clock domains in a network. Host 20 is the source of a serial data stream DATA, and device 30 is the destination of the serial data stream DATA. Host 20 operates in a first clock domain having a first frequency f1, repeater 10 operates in a second clock domain having a second frequency f2, and device 30 operates in a third clock domain having a third frequency f3.
Repeater 10 generally includes a first receiver 12 for receiving serial data stream DATA from host 20, a first transmitter 14 for transmitting serial data stream DATA to device 30, and a first-in-first-out (FIFO) memory or elastic buffer 16 for buffering the serial data stream between receiver 12 and transmitter 14. Repeater 10 also generally includes a second receiver 22 for receiving a second serial data stream from another source (i.e., a host or device, including device 30, other than host 20) and a second transmitter 24 for transmitting the second serial data stream to another destination (i.e., a host or device, including host 20, other than device 30).
Receiver 12 generally includes a clock data recovery circuit, decoding circuitry and serial-to-parallel data conversion circuitry. Transmitter 14, on the other hand, generally includes encoding circuitry, parallel-to-serial data conversion circuitry and a transmitter clock for transmitting data to an external destination. Elastic buffer 16 has a first write port (and associated data writing circuitry) configured to write data received from receiver 12 into memory cells in the elastic buffer at a first internal frequency. Elastic buffer 16 also has a first read port (and associated data reading circuitry) configured to read data from memory cells in the elastic buffer at a second internal frequency, which is generally about the same as the first internal frequency.
Data transmitted across conventional serial transmission media (e.g., copper wire, optical fiber) having a certain minimum length is reasonably likely to have some jitter. In some cases, the jitter in the incoming data stream may cause glitches, false data, incorrect processing operations (such as incorrect clock recovery adjustments), and other data transmission errors. In such cases, a clock signal recovered from the incoming data stream also has jitter that is carried forward, reproduced or otherwise incorporated from the jitter in the incoming data stream. However (and at least in part to minimize the jitter introduced into a data stream by transmission media), transmitter 14 generally transmits data using a “clean,” or substantially jitter-free clock signal. Thus, unless repeater/transceiver 10 is configured to remove such jitter or reduce its effects, data communications using the repeater/transceiver 10 may be unacceptably error-prone. Thus, conventional approaches to generating a “clean” transmitter clock signal have generally tried to keep the transmitter clock and the recovered clock somewhat independent of each other. For example, even when the transmitter clock and the recovered clock have the same nominal frequency in a given application, to minimize any jitter that may be propagated by the recovered clock, designers sometimes lock the transmitter clock to (and/or adjust the transmitter clock with reference to) a third clock (although the third clock be adjusted with respect to the recovered clock). Thus, elastic buffer 16 not only temporarily stores data during data transfer across time domains (including from a “jittery” clock domain to a “clean” clock domain), but in effect, can also buffer any phase and/or frequency difference between the two different clock domains.
However, elastic buffer 16 generally requires a number of clock cycles to store and retrieve data, thus introducing latency into the data communication path in the repeater 10. Furthermore, the memory cells in elastic buffer 16 generally must be stored and retrieved in blocks, typically of a multiple of 8 bits (e.g., 8, 16, 32 or 64 bits). This structure in the FIFO memory array necessitates deserializer and serializer circuitry in the receiver and transmitter, respectively. Deserializer and serializer circuitry uses rows or banks of latches or registers for temporary storage of data as it is converted from one form to another, thereby introducing further latency into data communications through repeater 10.
As is known in the art, latency increases the overall time for data communications and reduces throughput (i.e., bits per second sent through the repeater). Under certain conditions and/or in certain applications, the latency introduced by elastic buffer 16, receiver 12 and transmitter 14 may be unacceptably high. Therefore, a need exists to reduce latency in high-speed repeaters.